Synthesis and Implementation of 3D IIR Filter As a Processing Element of Systolic Array Architecture

The parallel processing systolic array architecture is designed for the real time VLSI spatio temporal 3D Infinite Impulse Response (IIR) frequency planar filter to achieve high throughput of one frame per clock cycle (OFPCC). To reduce the circuit complexity by designing the architecture, that is based on differential form transfer function of a 3D IIR frequency planar filter. The 3D Look Ahead(LA) form of the transfer functions along with retiming techniques is used to maximize the speed of the architecture. This array architecture is used for a real-time implementation of 3D IIR frequency planar filters, which is operating at radio frequency frame rate. This 3D IIR frequency planar filter acts as a building block for 3D IIR digital filters having beamand coneshaped pass bands, which is required for smart antenna array beamforming applications. The proposed 7X7 systolic array architecture of 3D IIR frequency planar filter is synthesized and implemented on Virtex5 xc5vlx50tff1136-1 FPGA device and its achieves maximum operating frequency of 109.016MHz. KEYWORDS— Systolic array, Multidimensional signal processing, Frequency Planar filter, 3D LA Techniques, Retiming Techniques.